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device operating t emperature range package semiconductor technical data monomax black and white tv subsystem ordering information MC13001Xp mc13007xp t a = 0 to +70 c plastic dip order this document by MC13001X/d p suffix plastic package case 710 1 motorola analog ic device data
the monomax is a single chip ic that will perform the electronic functions of a monochrome tv receiver , with the exception of the tuner , sound c hannel , a n d p owe r o utpu t s tages . t h e m c13001x p a nd mc13007xp will function as a dropin replacement for the mc13001p and mc13007p, but some external if components can be removed for maximum benefit. if agc range has been increased, video output impedance lowered, and horizontal driver output current capability increased. ? full performance monochrome receiver with noise and video processing (black level clamp, dc contrast, beam limiter) ? video if detection onchip (no coils, no pins, except inputs) ? noise filtering onchip (minimum pins and externals) ? oscillator components onchip (no precision capacitors required) ? MC13001Xp for 525 line ntsc and mc13007xp for 625 line ccir ? low dissipation in all circuit sections ? high performance vertical countdown ? 2loop horizontal system with low power startup mode ? noise protected sync and gated agc system ? designed to work with tda1190p or tda3190p sound if and audio output devices figure 1. basic elements of the system vertical integrator vertical sync separator window control & reset if in if in rf agc rf agc delay agc flyback horizontal sync separator v cc 3 5 11 10 9 15 7 18 19 +8.0v out 4 2 6 26 25 27 vif if decoupling sound if 28 contrast beam limit 24 8 23 22 21 20 17 video out agc filter vertical sync vertical out vertical feedback vertical size horizontal out 13 12 14 horizontal phase detector 1 horizontal frequency video if vif detector video process blank buffer video process agc sync rf agc agc agc feed forward sync separator noise process vertical clock 525 vertical ramp horizontal phase detector 2 regulator 2 31.5 khz oscillator 2 vertical preamp phase detector 1 variable slicer horizontal buffer flyback buffer black clamp horizontal phase detector 2 ? motorola, inc. 1995
MC13001X mc13007x 2 motorola analog ic device data maximum ratings (t a = 25 c, unless otherwise noted.) rating symbol value unit power supply voltage pin 18 v cc +16 vdc power dissipation p d 1.0 w horizontal driver current pin 17 i hor 20 ma rf agc current pin 11 i rfagc 20 ma video detector current pin 24 i vid 5.0 ma vertical driver current pin 22 i vert 5.0 ma auxiliary regulator current pin 19 i reg 35 ma thermal resistance junctiontocase r q jc 60 c/w maximum junction temperature t j 150 c storage temperature range t stg 65 to + 150 c operating temperature range t a 0 to + 70 c recommended operating conditions rating symbol value unit horizontal output drive current i hor 10 ma rf agc current i rfagc 10 ma regulator current i reg 20 ma electrical characteristics (v cc = 11.3 v, t a = 25 c) characteristics symbol min typ max unit power supply current (pins 18, 19) i cc 44 76 ma regulator voltage (pin 19) v reg 7.2 8.2 8.8 vdc horizontal specifications oscillator frequency (nominal) (pin 12) f hor(nom) 13 19 khz oscillator sensitivity 230 hz/ m a startup frequency (i 18 = 4.0 ma) f hor 10 +10 % oscillator temperature stability (0 ta 75 c) 50 hz phase detector 1 (charge/discharge current) (nonstandard frame) (standard frame) i f 1 900 400 m a phase detector 2 (charge/discharge current) v f 2 +1.0 0.6 ma phase detector 1 (output voltage limits) v f 1 7.5 (max) 2.5 (min) vdc phase detector 2 (output voltage limits) v f 1 7.7 (max) 1.5 (min) phase detector 1 (leakage current) 2.0 m a phase detector 2 (leakage current) 3.0 horizontal delay range (sync to flyback) 18 (max) 5.0 (min) m s horizontal output saturation voltage (i 17 = 15 ma) v 17(sat) 0.3 vdc phasedetector 1 (gain constant) (outoflock) (inlock) 5.0 10 m a/ m s horizontal pullin range 500 750 hz
MC13001X mc13007x 3 motorola analog ic device data electrical characteristics (continued) (v cc = 11.3 v, t a = 25 c) characteristics symbol min typ max unit vertical specifications output current (pin 22) i 22 0.6 ma feedback leakage current (pin 21) i 21 6.0 m a feedback maximum voltage v 21 5.1 vdc ramp retrace current (pin 20) i 20 500 900 m a ramp leakage current (pin 20) 0.3 m a if specifications regulator voltage v 4 7.5 vdc input bias voltage v 2,6 4.2 input resistance r in 6.0 k w input capacitance (v agc pin 8 = 4.0 v) c in 2.0 pf sensitivity (v 8 = 0 v, 400 hz 30% mod, v 28 = 0.8 v pp ) 80 m v rms bandwidth bw 75 mhz video specifications zero carrier voltage (see figure 5) (pin 28) 7.0 vdc output voltage (see figure 6) (pin 24) white to back porch 1.4 v differential gain 6 % differential phase (ire test method) 4 degrees contrast bias current (pin 26) i 26 10 m a contrast control range 14:1 beam limiting voltage (pin 27) v 27 1.0 vdc agc & sync rf (turner agc output current (v 11 = 5.5 v) i 11 5.0 ma agc delay bias current i 10 10 m a agc feedforward current i 9 1.0 ma agc threshold (sync tip at pin 28) v 28 4.7 5.1 vdc sync separator operating point v 7 4.2 vdc sync separator charge current i 7 5.0 ma figure 2. monomax agc characteristics figure 3. video output response agc voltage, pin 8 (v) if gain reduction (db) agc feedfor ward, pin 9 (v) 0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10 relative attenuation (db) video output response (mhz) 0 10 20 30 40 50 3 2 1 0 1 2 3 4 5 6 5.0 4.0 3.0 2.0 1.0 0 (pin 9) video out (pin 24) with max contrast sound if out (pin 28)
MC13001X mc13007x 4 motorola analog ic device data general description the v ideo if amplifier is a fourstage design with 80 m v, sensitivity. it uses a 6.2 v supply decoupled at pin 4. the first two stages are gain controlled, and to ensure optimum noise performance, the first stage control is delayed until the second stage has been gain reduced by 15 db. t o bias the amplifier , balanced dc feedback is used which is decoupled at pins 2 and 6 and then fed to the input pins 3 and 5 by internal 3.9 k resistors. the nominal bias voltage at these input pins is approximately 4.2 vdc. the input, because of the high if gain, should be driven from a balanced dif ferential source. for the same reason, care must be taken with the if decoupling. the if output is rectified in a full wave envelope detector and detector nonlinearity is compensated by using a similar nonlinear element in a feedback output buf fer amplifier. the detected 1.9 v pp video at pin 28 contains the sound intercarrier signal, and pin 28 is normally used as the sound takeoff point. the video frequency response, detector to pin 28, is shown in figure 3 and the detector intermodulation performance can be seen by reference to figure 4. t ypical pin 28 video waveforms and voltage levels are shown in figure 5. the video processing section of monomax contains a contrast control, black level clamp, a beam current limiter and composite blanking. the video signal first passes through the contrast control. this has a range of 14:1 for a 0 v to 5.0 v change of voltage on pin 26, which corresponds to a change of video amplitude at pin 24 of 1.4 v to 0.1 v (black to white level). the beam current limiter operates on the contrast control, reducing the video signal when the beam current exceeds the limit set by external components. as the beam current increases, the voltage at pin 27 moves negatively from its normal value of 1.5 v , and at 1.0 v operates the contrast control, thus initiating beam limiting action. after the contrast control, the video is passed through a buf fer amplifier and dc is restored by the black level clamp circuit before being fed to pin 24 where it is blanked. the black level clamp, which is gated aono during the second half of the flyback, maintains the video black level at 2.4 v 0.1 v under all conditions, including changes in contrast, temperature and power supply. the loop integrating capacitor is at pin 25 and is normally at a voltage of 3.3 v . the frequency response of the video at pin 24 is shown in figure 3 and it is blanked to within 0.5 v of ground. 10 20 30 40 50 relative product attenuation (db) relative 41.25 mhz input level (db) 4.5 mhz 2.66 mhz 920 khz reference = 3.58 mhz figure 4. detector products 10 0 10 20 30 40 50 60 45.74 mhz = 25 mvrms 42.17 mhz = 12.5 mvrms 41.25 mhz = relative to 41.25 mhz = 45.75 mhz 7.0 v 5.1 v 3.6 v 87.5% 25% zero carrier back porch agc threshold noise threshold figure 5. pin 28 sound output 3.8v 2.4v 1.7v max. contrast max. blanking level min. contrast back porch figure 6. pin 24 video output the agc loop is a gated system, and for all normal variations of the if input signal, maintains the sync tip of a noise filtered video signal at a reference voltage (5.1 v pin 28). the strobe for the agc error amplifier is formed by gating together the flyback pulse with the separated sync pulse. integration of the error signal is performed by the capacitor at pin 8, which forms the dominant agc time constant. improved noise performance is obtained by the use of a gated agc system, noise protected by a dc coupled noise canceling circuit. the false agc lock conditions, which can result from this combination, are prevented by an antilockout circuit connected to the sync separator at pin 7. agc lockout conditions, which occur due to large rapid changes of signal level are detected at pin 7 and recovery is ensured under these conditions by changing the agc into a mean level system. the voltage at pin 10 sets the point at which tuner agc takeover occurs and positive going tuner control, suitable for an npn rf transistor , is available at pin 11. the maximum output is 5.5 v at 5.0 ma. a feedforward output is provided at pin 9. this enables the agc control voltage to be ac coupled into the tuner takeover control at pin 10. the coupling allows additional if gain reduction d urin g s igna l t ransien t c onditions , t hus compensating for variations of agc loop gain at the tuner agc takeover point. in this way the agc system stability and response are not degraded. the previously mentioned noise protection is ef fected by detecting negativegoing noise spikes at the video detector output. a dc coupled detector is used which turns on when a noise spike exceeds the video sync tip by 1.4 v . this pulse is then stretched and used to cancel the noise present on the delayed video at the input to the sync separator . cancellation is performed by blanking the video to ground. complete cancellation of the noise spike results from the stretching of the blanking pulse and the delay of the noise spike at the input to the sync separator . protection of both the horizontal pll and the agc stems from the fact that both circuits use the noise cancelled sync for gating.
MC13001X mc13007x 5 motorola analog ic device data the composite sync is stripped from a delayed and filtered video in a peak detecting type of sync separator . the components connected to pin 7 determine the slice and tilt levels of the sync separator . for ideal horizontal sync separation and to ensure correct operating of agc anti lockup circuit, a relatively short time constant is required at pin 7. this time constant is less than optimum for good noise free vertical separation, giving rise to a vertical slice level near sync tip. an additional longer timeconstant is therefore coupled to the first via a diode. with the correct choice of time constants, the diode is nonconducting during the horizontal sync period, but conducts during the longer vertical period. this connects the longer time constant to the sync separator for the vertical period and stops the slice level from moving up the sync tip. the separated composite sync is integrated internally, and the time constant is such that only the longer period vertical pulses produce a significant output pulse. the output is then fed to the vertical sync separator , which further processes the vertical pulse and provides increased noise protection. t h e s electio n o f t h e e xterna l c omponents connected to the vertical separator at pin 23 permits a wide range of performance options. a simple resistor divider from the 8.2 v regulated supply gives adequate performance for most conditions. the addition of an rc network will make the slice level adapt to varying sync amplitude and give improved weak signal performance. a resistor to the agc voltage on pin 9 enables the sync slice level to be changed as a function of signal level. this further improves the low signal level separation while at the same time giving increased impulse noise protection on strong signals. horizontal oscillator the horizontal pll (see figure 7) is a twoloop system using a 31.5 khz oscillator which after a divider stage is locked to the sync pulse using phase detector 1. the control signal derived from this phase detector on pin 13 is fed via a highvalue resistor to the frequencycontrol point on pin 12. the same divided oscillator frequency is also fed to phase detector 2, where the flyback pulse is compared with it and the resulting error used to change a variable slice level on the oscillator ramp waveform. this therefore changes the timing of the output square wave from the slicer and hence the timing of the buf fered horizontal output on pin 17 (see figure 8). the error on phase detector 2 is reduced until the phasing of the flyback pulse is correct with respect to the divided oscillator waveform, and hence with respect to the sync pulse. 15 13 7 17 200 mv pp 50 mv pp 4.5 v 6.0 v 2.0 v 0 v +0.9 v 0 v 0.7 v figure 8. horizontal waveforms to improve the pullin and noise characteristics of the first pll, the phase detector current is increased when the vertical lock indicator signals an unlocked condition and is decreased when locked. this increases the loop bandwidth and pullin range when out of lock, and decreases the loop bandwidth w he n i n l ock , t hu s i mprovin g t h e n oise performance. in addition, the phase detector current during the vertical period is reduced in order to minimize the disturbance to the horizontal caused by the longer period vertical phase detector pulses. 31.5khz oscillator 12 13 15 17 14 slice divide by 2 divide by 2 slice output vary slice level (phase) phase detector 1 deflection flyback phase detector 2 vary frequency sync figure 7. horizontal oscillator systems
MC13001X mc13007x 6 motorola analog ic device data the oscillator itself is a novel design using an onchip 50 pf silicon nitride capacitor which has a temperature drift of only 70 ppm/ c and negligible long term drift. this, in conjunction with an external resistor , gives a drift of horizontal frequency of less than 1.0 hz/ c i.e., less than 100 hz over the full operating temperature range of the chip. the pullin range of the pll is about 750 hz, so normally this would eliminate the need for any customer adjustment of the frequency. the second significant feature of this design is the use of a virtual ground at the frequency control point which floats at a potential derived from a divider across the power supply and this is the same divider which determines the endpoints of the oscillator ramp. the frequency adjustment which is necessary to take up tolerances in the onchip capacitor is fed in as a current to this virtual ground, and when this adjustment current is derived from an external potentiometer across the same supply there is no frequency variation with supply v oltage . m oreover , u sin g t h e v oltag e f rom a potentiometer for the adjustment instead of the simple variable resistor normally used in rc oscillators makes the frequency independent of the value of the potentiometer and hence its temperature coef ficient. the frequency control current from the first phase detector is fed into this same virtual ground, and as the sensitivity of the control is about 230 hz/ m a, a high value resistor can be used (680 k w ) which can be directly connected to the phase detector filter without significant loading. this oscillator operates with almost constant frequency to below 4.0 v and as the total pll system consumes less than 4.0 ma at this voltage, this gives an ideal startup characteristic for receivers using deflectionderived power supplies. the flyback gating input is on pin 15 which is internally clamped to 0.7 v in both directions and requires a negative input current of 0.6 ma to operate the gate circuit. this input can be a raw flyback pulse simply fed via a suitable resistor. vertical system an output switching signal is taken from the 31.5 khz oscillator to clock the vertical counter which is used in place of a conventional vertical oscillator circuit. the counter is reset by the vertical sync pulse, but the period during which it is permitted to reset is controlled by the window control. normally, when the counter is running synchronously , the window is narrow to give some protection against spurious noise pulses in the sync signal. if the counter output is not coincident with sync however , after a short period the window opens to five reset over a much wider count range, leading to a fast picture roll towards lock. at weak signal, i.e., less than 200 m v if input, the vertical system is forced to narrow mode to give a steadier picture for commonly occurring types of noise. the vertical sync, gated by the counter , then resets a ramp g enerato r o n p i n 2 0 a n d t h e 1 . 5 v pp r am p i s buffered to pin 22 by the vertical preamplifier . a dif ferential input to the preamp on pin 21 compares the signal generated across the resistor in series with the deflection coils with the generated ramp and thus controls shape and amplitude of the coil current. the basic block diagram of the countdown system is shown in figure 9. the 31.5 khz (2f h ) clock from the horizontal oscillator drives a 10stage counter circuit which is normally reset by the vertical sync pulse via the sync gate, ``or'' gate and d flipflop. this d input is also used to initiate discharge of the ramp capacitor and hence causes picture flyback. 2f h clock 0 20 blanking latch 10 stage counter counter reset 514526 ``narrow'' 384544 ``wide'' h/4 delay coincidence detector vertical sync coinc 8h/2 delay 2h/2 delay window control sync gate/ ramp latch d flipflop (delay) define window for sync to ramp pulldown clock blanking pulse to ``wide'' coinc to ``narrow'' d figure 9. monomax vertical countdown
MC13001X mc13007x 7 motorola analog ic device data the period during which sync can reset the counter and cause flyback is determined by the window control which defines a count range during which the gate is open. one of two ranges is selected according to the condition of the signal. the normal anarrowo range is 514 to 526 counts for a 525 line system and is selected after the coincidence detector indicates that the reset is coincident, twice in succession, with the 525 count from the counter . when the detector indicates noncoincidence 8 times in succession, then the window control switches to the awideo mode (384 to 544 counts) to achieve rapid resynchronization. for the 625 line version the counts are 614 to 626 for narrow mode and 484 to 644 for wide mode. note that the or gate after the sync gate is used to terminate the count at the end of the respective window if a sync pulse has not appeared. this method accepts nonstandard signals almost in the same way as a conventional triggered rc oscillator and has a similar fast lockin time. however , the use of a window control on the counter reset ensures that when locked with a normal standard broadcast signal the counter will reject most spurious noise pulse. the blanking output is provided from a latch which is set by the counter reset pulse and terminated by count 20 from the counter chain. 7.0 v 6.0 v 2.5 v 2.0 v 0 v 4.0 v 500 mv pp 1.0 v pp 23 20 22 21 figure 10. vertical waveforms power supply the power supply regulator , although of simple design, provides two independent power supplies one for the horizontal pll section and the other for the remainder of the chip. the supplies share the same reference voltage but the design of the main regulator is such that it can be switched on independently to give minimum loading on the ableedo v oltag e s ourc e d urin g s tartu p p has e o f a defectionderived supply system. + v bl r bl = v bl 8 4 x 10 3 horizontal startup bleed main 12 v supply i ext 8.2 v to external circuits r 6 r bl 18 19 8.2v to all monomax circuits except horizontal 8.2 v to horizontal system r 1 q 6 d 1 z 1 q 7 q 1 q 4 r 5 r 4 q 2 r 3 q 3 r 2 q 5 d 2 figure 11. power supply circuit i ext (ma) < 5.0 r 6 ( w ) 150 20 82 35 68
MC13001X mc13007x 8 motorola analog ic device data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v 2 v 4 v 6 v 7 i 7 v 8 i 9 i 10 i 11 i 12 v 01 i 01 i 02 v 02 10nf 10nf 10nf 10nf 180k 820 10nf 47k 470 82k 91k 10nf 10nf v 28 v 27 i 26 i 22 i 20 i cc v 17 100 56k 22k 0.1nf 0.1nf v reg v reg 12k 2.2k 50nf 470k 8.2k 220 12v 2.2nf v 21 12v 27k 750k 0.1 m f 12v v reg source 8.2v 220 12v 120v 0.1nf 22k 330 5.0v flyback pulse 6.6k 40 detected video 36k 2.7k 12k 1.0k 10k 3.9k 8.0k 3.5k 250 500 pin 19 regulated supply blanking 2.5k video same as pin 3 same as pin 2 sync video vertical sync integrated sync 100 4.7k 6.2v 5.0k vertical countdown regulated supply 35k 100 10k horizontal supply 3.0k 3.0v 5.0k 300 agc gate 470 + 0.1 m f figure 12. test circuit diagram
MC13001X mc13007x 9 motorola analog ic device data horiz freq see application note an879 for further information. +8.2v 39k to tda1190p sound if 82k 1 4.7 m f 10 high voltage winding contrast +8.2v black level clamp 47k 1.0 f m 220 video out 1.2k +8.2v vert feedback +24v +12v +120v +120v +120v 2.2k 470 k vert drive vert size 0.05 3.3m +8.2v v reg 1.0m 150 0.1 0.1 v cc 27k startup resistor 33k horiz drive flyback v pk r fb r fb = v pk 2 k w MC13001X monomax 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v rf 10nf 10nf 50nf video if in +8.2v 2.7m 1.8m 2.2k 50nf 23 pin 9 120k 1.0 m f 470k 680 vertical sync, optional components for extra performance with low signal strength. sync separator components 1.0 m f 0.1nf rf agc delay 20k 8.2v 39k +8.2v rf agc horiz freq horiz phase det. 1 horiz phase det. 2 10nf 2% metal film or metal oxide 100k 360k 91k 100pf 20% 10nf tuner 680k 22nf vert sync 50nf 0.47 f m 0.33 m f 8.2k figure 13. simplified application
MC13001X mc13007x 10 motorola analog ic device data p suffix plastic package case 71002 issue c outline dimensions notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 seating plane 15 14 28 m a b k c n f g d h j l dim min max min max inches millimeters a 36.45 37.21 1.435 1.465 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa / europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 MC13001X/d ?

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